PS.
Design Verification Engineer

Hello, I’m
Preetham S.

Building confidence in digital designs.

I build reusable UVM environments, verify protocols, and drive coverage closure. My work combines SystemVerilog, assertions, and constrained-random verification to check digital IP.

Explore my projects

Bangalore, India · 1+ year of verification experience

Portrait of Preetham S wearing a dark blazer
Preetham S / Design Verification Engineer

01 / Academic projects

Verification
in practice.

UVM testbenches built around corner cases, protocol correctness, and measurable coverage.

FIFO Verification using UVM

A complete verification environment for a configurable FIFO, with a reusable agent architecture, reference model, scoreboards, assertions, and functional coverage.

  • Verified overflow, underflow, and boundary conditions.
  • Tested simultaneous read and write operations.

>95% functional coverage
100% code coverage

SystemVerilogUVMSVA

APB-to-AXI Bridge Verification using UVM

A UVM testbench for an APB-to-AXI bridge, with transaction-level scoreboarding to compare APB requests with AXI responses.

  • Verified protocol conversion, burst handling, and address alignment.
  • Checked error propagation.
  • Created constrained-random scenarios for back-to-back and stress transactions.
UVMAPB / AXIScoreboarding

02 / Experience

From testbench
to closure.

Harman Connected Services

Currently Wipro

July 2025 – Present

Bangalore, India

Junior Associate Software Engineer
Design Verification

  • Develop scalable UVM environments for digital IP, including reusable agents, sequencers, and scoreboards.
  • Design constrained-random stress sequences, achieving over 95% functional coverage and driving coverage closure.
  • Implement SystemVerilog Assertions for AXI, AHB, and APB protocol checking and design rule validation.
  • Maintain regression suites and debug simulation failures with QuestaSim and VCS.
  • Collaborate with RTL designers to resolve functional and timing issues.

03 / About & education

Curious about
every corner case.

I’m a Design Verification Engineer based in Bangalore, with a foundation in Electronics and Communication Engineering and hands-on experience in protocol verification, simulation debugging, and automation.

Education

Sir M Visvesvaraya Institute of Technology

Bachelor of Engineering
Electronics and Communication Engineering

December 2021 – May 2025 · Bangalore

CGPA: 8.5 / 10

04 / Technical skills

The tools behind
the work.

Languages

SystemVerilog · Verilog · Python · C

Verification

UVM · Constrained-random verification · Functional coverage · Coverage closure · SVA

Protocols

AXI4 · AHB · APB · SPI · I2C · UART

EDA tools

QuestaSim · Synopsys VCS · Cadence Xcelium · SpyGlass

Static checks

Lint · CDC · X-propagation

Scripting & automation

Python · Shell · Git

05 / Contact

Let’s connect.

For design verification opportunities, engineering collaborations, and conversations about digital systems.

Email me
Emailpreethams7works@gmail.comLinkedInlinkedin.com/in/preethams7GitHubgithub.com/preetham-s7